Memories such as random access and read only memories which are randomly addressable are usually arranged as a matrix of storage locations or groups of storage locations which are addressable by row and by column. Various organizations of memory locations are possible. For example, a 1Mbit memory can be arranged as 256K words of 4 bits addressable on 512 rows and 512 columns, so that addressing a specific row and column gives access to a group of 4 storage locations. An alternative organization is as 128K words of 8 bits addressable either on 512 rows and 256 columns or 256 rows and 512 columns, so that addressing a specific row and column gives access to a group of 8 storage locations. It will be appreciated that these are just two of many possible organizations.
There are many different types of randomly addressable memories. Examples are read only memories (ROMs), programmable ROMs (PROMs), static random access memories (SRAM), dynamic RAM (DRAM) and video RAM (VRAM), the latter being a specific type of DRAM. These memories are normally accessed by inputting address signals which first select a row and then select a column within the memory, in response to timing signals termed RAS (row address strobe) and CAS (column address strobe), respectively. During such normal accessing of the RAM the row address cycles alternate with column address cycles, each pair of row and column cycles allowing access to the bit or bits having a specified row and column address.
In some memories however, an additional access method, generally termed "page mode", is provided in accordance with which multiple column cycles are performed within a single row cycle. The term "static column mode" has been used for this type of access method. However, the term "page mode" is widely understood in the art as being a generic term covering this type of access method Conventionally, a row address is selected for a page mode row cycle and, within that row cycle, multiple column cycles are performed to access the memory at selected column addresses in that row. By avoiding the need for a new row address strobe to be provided each memory access, fast access can be had to data occurring within a single row.
One application for RAM is as an all points addressable (APA) display memory in a display system. In modern APA raster displays, an image to be viewed is stored point-by-point as picture element (pixel) data in a memory subsystem frame buffer, comprised of dynamic random access memory (DRAM) or video random access memory (VRAM). These designs allow arbitrary update of pixel contents for display of arbitrarily complex images.
The information stored is either periodically refreshed to restore the image on the video monitor or is updated to modify the displayed image. For raster scan displays, horizontal line updates generally occur in page mode, wherein data on an accessed row is updated in multiple column locations, corresponding to adjacent pixels on a scan line, for enhanced update bandwidth. However, vertical line updates generally require multiple sequential row accesses to perform image modification at random cycle time performance, as much as four times longer than that of page mode update.
Referring to FIG. 1, assume that pixel data for a horizontal line is stored along adjacent column locations in a row of memory (e.g. C[a], C[a+1], C[a+2], etc.) while vertical lines are stored in a column across multiple rows (e.g. C[a], C[b], C[c], etc.). It will be appreciated that other storage conventions may be used In this general case, page mode can be used for plotting straight horizontal lines by simply accessing sequential storage cells on a row in page mode. However, page mode provides no benefit for vertical lines, and little, if any benefit for lines at intermediate angles or for curves. As shown in FIG. 2, continuous RAS cycles are needed to access each pixel, C[a], C[b], C[c], along a given vertical line. As a result, performance decreases dramatically for continuous row-to-row accesses.
The primary problem the inventors had to address was a solution to the spatial difference in updating or plotting performance of a display. On analyzing the problem it was realized that it resulted from the basic hardware constraints of random access memories with page mode.